Memories are conventionally organized into matrices of storage cells. The cells of a given column are connected to one or more bit lines. In the non-volatile memories (of the ROM, EPROM, EEPROM or Flash EPROM type), the cells are connected to a bit line. In static random-access memories (SRAMs) these cells are connected to two bit lines that are complementary to each other. The cells of a given row are connected to a word line. The bit line (or complementary bit lines) make it possible to transmit information on the state of a storage cell located at the intersection between this bit line and a selected word line.
The read circuits are connected to the bit lines of the columns, possibly by means of a multiplexer if one read circuit is used for several columns. Typically, the reading of a cell includes producing a logic signal representing the value of an electrical current that goes through this cell. This value depends on the state of the cell. If we consider, for example, a non-volatile memory, the cells may have a state called a blank state (or a programmed state depending on the convention chosen) in which they can let through a current, and a state called a programmed state (or blank state depending on the convention chosen) in which they counter the passage of the current. To read the information on the state of a cell, the equivalent capacitance of the bit line to which this cell is connected is used. This capacitance is generally in the range of one picofarad. It is sought to detect the presence of a current for the charging or discharging of the bit line connected to the cell.
In general, a differential reading is used. Thus, in the non-volatile memories, a reference line similar to the bit line is generally used. This reference line conducts a reference current during the read operation. In SRAMs, the two complementary bit lines connected to the cells are used. The reading is done by using a differential amplifier to compare the potentials present, firstly, in the bit line and, secondly, in the reference line or the complementary bit line. These potentials vary according to whether these lines are charged or discharged.
One problem arising out of this type of circuit is the influence of the value of the equivalent capacitive load of the line or lines on the time required for read access to the contents of the cells. This equivalent capacitive load is related to the geometrical parameters of the lines and the state of the cells connected to these lines. The greater this load, the greater is the time needed for the reading. Since the access time is variable, there can be no certainty that a read operation has been performed except after a period of time corresponding to the reading at theoretical maximum equivalent load, even if the reading may, in practice, be faster.
It is also necessary to take into account the differences in capacitive load between the lines. If the lines are charged differently, the times of stabilization of the potentials on these lines are different. In addition to the times of stabilization of the potentials, it is also appropriate to take into account the influence of the difference in load on the operation of the reading device connected to the lines. If the device is sensitive to this influence, then it is necessary to plan for an additional time margin in the guaranteed read access time.
Finally, the current trend is to propose circuits that can be custom-built by means of modules, especially circuits comprising memories with sizes suited to the applications. In practice, the influence of the capacitive load makes it necessary to adapt the implementation of the read circuits on an individual basis, in taking into account the size of the memory to be made.